Home Company Info Product List Contact Details
Homeproduct Directory

AES-E

AES-E
company Acro Information Technology Ltd.
Categories LED Displays
Update2010-07-29
Original RegionChina
AES-E
 
 
   
Home   |   EDA  |   IP Core   |   Design Service  |   News   |   Partners   |   Contact us  |   |  

HomeSolutionsIPEncryption AES_E Advanced Encryption Standard Encoding Core

Description | Features | Applications | Block Diagram | Implementation | Export Permits | Deliverables

The AES_E core implements Rijndael encoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for128-, 192-, and 256-bit key lengths.

Features Encrypts using the AES Rijndael Block Cipher Algorithm Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST) Processes 128-bit data in 32-bit blocks Employs user-programmable key size of 128, 192 or 256 bits Smallest version supports a single block cipher mode, Electronic Codebook (ECB); these modes can be added as needed: Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB) and Counter (CTR) Works with a pre-expended key or can integrate the optional key expansion function Simple, fully synchronous, reusable design Available as fully functional and synthesizable VHDL or Verilog, or as a netlist for popular programmable devices Complete deliverables include test benches Applications Protected network routers Electronic financial transactions Secure wireless communications Secure video surveillance systems Encrypted data storage Block Diagram
Implementation Results Device Utilization and Performance

Throughput with
128-bit key

Table 3 Representative ASIC Performance Figures

Throughput Comparisons
Export Permits
CubaIranIraqLibya
North KoreaSudanSyria 
Deliverables HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs) Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core Simulation script, vectors, expected results, and comparison utility Synthesis script (ASICs) or place and route script (FPGAs) Comprehensive user documentation, including detailed specifications and a system integration guide
   
 

Copyright Acro Design Systems Ltd. | Website manage |
Copyright © 2005-2006www.acro-da.com All rights reserved

AES-E on sale

Products Showcase

See more products from this supplier.

Do you want to show products of your own company? Join FREE now!

You may also be interested in: